The first related application discloses a new form or type of integrated circuitry which effectively and efficiently combines and maximizes the various advantages of processors, application specific integrated circuits (“ASICs”), and field programmable gate arrays (“FPGAs”), while minimizing potential disadvantages. The first related application illustrates a new form or type of integrated circuit (“IC”), referred to as an adaptive computing engine (“ACE”), which provides the programming flexibility of a processor, the post-fabrication flexibility of FPGAs, and the high speed and high utilization factors of an ASIC. This ACE integrated circuitry is readily reconfigurable or adaptive, in advance, in real-time or potentially slower, is capable of having corresponding, multiple modes of operation, and further minimizes power consumption while increasing performance, with particular suitability for low power applications, such as for use in hand-held and other battery-powered devices.
The adaptive computing engine (“ACE”) circuit of the first related application, for adaptive or reconfigurable computing, includes a plurality of heterogeneous computational elements coupled to an interconnection network, rather than the homogeneous units of FPGAs. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time or potentially slower to adapt and re-adapt (configure and reconfigure) the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. In turn, this configuration and reconfiguration of heterogeneous computational elements, forming various computational units and adaptive matrices (or adaptive nodes), in real-time or across time, generates the selected operating mode of the ACE integrated circuit, for the performance of a wide variety of tasks.
This ACE integrated circuit, as indicated above, is controlled by a series or sequence of bits, referred to as “configuration information”, which generates the configurations and reconfigurations which provide and create one or more operating modes for the ACE circuit, such as wireless communication, radio reception, personal digital assistance (“PDA”), MP3 music playing, or other desired functions.
Current system development tools, typically embodied as computer programs, do not address the particular needs and difficulties of designing ACE circuitry, and developing and scheduling configuration information to allow the ACE IC to perform a selected operating mode. As a consequence, a need remains for a suite of development tools which may design and develop ACE circuitry, adapt one or more algorithms for performance on ACE circuitry, schedule a selected algorithm for execution on selected ACE computational elements, and generate a bit file (as configuration information) for control of the ACE circuitry for the selected operating mode.